The present invention relates to a flash memory device, and more particularly, to a program method which can reduce the threshold voltage distribution width of a flash memory device having a multi-level cell.
Currently, there is an increasing demand for semiconductor memory devices which can be electrically programmed and erased and does not require refreshing the data. Furthermore, to develop large capacity memory devices, there has been research done to increase the level of integration. Accordingly, there has been much research done into flash memories.
Flash memory is generally classified as NAND flash memory or NOR flash memory. The NOR flash memory has a structure in which memory cells are independently connected to bit lines and word lines. Its main advantage is a faster random access time. Meanwhile, the NAND flash memory has a structure in which a plurality of memory cells are connected in series and only one contact per cell string is required. Its advantage is the higher level of integration. Accordingly, the NAND type structure is generally used in high-integration flash memories.
In recent years, to further increase the degree of integration of flash memory, research has been done into storing more than one bit in one memory cell. This type of a memory cell is generally referred to as a “Multi-Level Cell (MLC)”. A memory cell of a single bit corresponding to the MLC is referred to as a “Single Level Cell (SLC)”.
In general, the threshold voltages (Vt) of the MLCs may be set to various states depending on the data being stored. In more detail, since 2-bit data can be programmed into the MLC, one MLC can store any one of four values (i.e., 1, 10, 01, and 00) with each binary value being assigned a threshold voltage (Vt) state.
The program methods of a MLC can be largely classified into two kinds. The first method performs three program operations using different program voltages at each time of the one-page program in order to implement four threshold voltage levels. In this case, the program time is three times greater than that of a SLC having the same capacity. Furthermore, since the voltage gap between the four threshold voltages is very narrow (0.7 to 0.8V), an Incremental Step Pulse Program (ISPP) voltage must be set to range from 0.15 to 0.2V during the program operation. This means that the ISPP voltage must be reduced in comparison with the SLC (about 0.5V). Therefore, the overall program time is 7 to 9 times greater than that of the SLC.
To solve the problem, a program method of allocating different row addresses to 2 bits programmed into one cell has been proposed. As shown in FIG. 1, upon first program, Least Significant Bit (LSB) data (“11”→“10”) of the 2 bits are programmed. Thereafter, upon second program, Most Significant Bit (MSB) data (“11”→“01” or “10”→“00”) are programmed. At this time, it is determined whether a current cell is “11” or “01” by reading a first page and different voltages are then applied to the bit lines.
If threshold voltage distributions of programmed cells of the MLC are increased, the gap between threshold voltages of each program state is further narrowed. This has a negative effect on the reliability of cell operation. It is therefore necessary to reduce the threshold voltage distributions of the cell. In general, the easiest method to reduce the threshold voltage distributions of ISPP is to lower the ISPP voltage. If the ISSP voltage is lowered, the required pulse number is increased. Accordingly, a problem arises because the program time is lengthened.